M.E/M.Tech DEGREE EXAMINATION, JANUARY 2010
First Semester
Computer Science and Engineering
CS9211 – COMPUTER ARCHITECTURE
(Common to M.Tech - Information Technology)
(Regulation 2009)
Time: Three hours Maximum: 100 Marks
Answer all the questions
Part A – (10*2=20 Marks)
1. What is hazard? State its types.
2. Mention the techniques available to measure the performance.
3. What is dynamic scheduling?
4. Give the limitation of ILP.
5. Distinguish between hardware and software speculation mechanisms.
6. What is static branch prediction?
7. What are the synchronization issues?
8. What is multithreading?
9. Define cache miss penalty?
10. What is RAID?
Part B – (5*16 = 80 Marks)
11. (a)How does one classify ISA? Discuss their design issues. (16)
(Or)
(b)What is pipelining? Explain various hazards involved in implementing pipelining. (16)
12. (a)Explain the instruction level parallelism with dynamic approaches. (16)
(Or)
(b)What is dynamic hardware prediction? Explain it in detail. (16)
13. (a)Explain the different hardware support for exposing ILP. (16)
(Or)
(b)Explain the different hardware support for more parallelism. (16)
14. (a)Explain distributed shared memory architecture with necessary life cycle diagram. (16)
(Or)
(b)(i)Differentiate software and hardware multithreading approaches. (8)
(ii)Explain the models of memory consistency. (8)
15. (a)How does one reduce cache miss penalty and miss rate? Explain. (16)
(Or)
(b)What are the ways available to measure the I/O performance? Explain each of them in detail. (16)